1. Field of the Invention
The present invention relates to a semiconductor device having a memory cell which is made up of one FG (Floating Gate) transistor and one selector gate transistor and, more particularly, to setting of the neutral threshold voltage of a cell transistor, and potentials applied to the cell transistor and selector gate transistor in read in a nonvolatile semiconductor memory device.
2. Description of the Related Art
As one kind of logic-embedded semiconductor memory device of which relatively high-speed read is required, there is proposed a nonvolatile semiconductor memory device having a memory cell which is made up of an FG transistor (cell transistor) and selector gate transistor. A memory cell of this type is described in, e.g., T. Ditewing et al., “An Embedded 1.2V-Read Flash Memory Module in a 0.18 μm Logic Process”, 2001 IEEE ISSCC Digest 2.4, pp. 34-35, Feb./2001. In a memory cell described in this reference, the drain of an FG transistor is connected to a bit line, its source is connected to the drain of a selector gate transistor, and the source of the selector gate transistor is connected to a source line. A signal output from a word line driver is supplied to the control gate of the FG transistor and the gate of the selector gate transistor to drive these transistors.
As a nonvolatile semiconductor memory device having a similar memory cell structure, there is known a NAND flash memory disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. H07-073688. The memory cell of the NAND flash memory is made up of a plurality of FG transistors and two selector gate transistors. The current paths of the FG transistors are series-connected, and the selector gate transistors are respectively interposed between the bit line and the drain side of the series-connected FG transistors and between the source line and their source side.
Since no selector gate transistor exists on the drain side in the memory cell described in the above reference, the memory cell is not influenced by the channel resistance of the selector gate transistor on the drain side in read. Hence, the cell current can be set large to read quickly.
On the other hand, a potential applied to an unselected bit line in write must be stopped in the selector gate transistor on the source side so as not to supply any current from the unselected bit line to the source line. For this reason, a stricter leakage current characteristic is required of the selector gate transistor than a NAND transistor, and demands have arisen for a measure against this.
Conventional setting of the neutral threshold voltage of a cell transistor and how to apply a control gate potential in read are as follows.
(1) A typical value of the neutral threshold voltage of a cell transistor is about 1 V.
(2) 0 V is applied to a control gate CG of the cell transistor in read.
(3) Write and erase conditions are set so that the threshold voltage of the cell transistor generally becomes about −2 V for “1” data and about 2 V for “0” data.
In a conventional nonvolatile semiconductor memory device described in the above reference, channel ion implantation is performed in the same step for a cell transistor and selector gate transistor in the manufacture. According to this manufacturing method, if the neutral threshold voltage of the cell transistor is set to about 1 V, the threshold voltage of the selector gate transistor becomes about 0.5 V. In write, a voltage of about 7 V is applied to the source/drain region of the selector gate transistor. When the cell transistor is at the neutral threshold voltage of about 1 V, a leakage current of a non-negligible magnitude may flow from the source line to bit line of the memory cell. The leakage current raises the potential of the bit line from a set value of −7 V, generating a write error.
In order to prevent this, the threshold voltage of the selector gate transistor is desirably set higher (e.g., about 1 V). However, the threshold voltage of the selector gate transistor and the neutral threshold voltage of the cell transistor change upon a change in channel ion implantation. It is important in terms of reduction of load on a negative-potential generation circuit to suppress small leakage of the bit line potential applied to an unselected cell to the source line in write. However, when the threshold voltage of the selector gate transistor is set high, the neutral threshold voltage of the cell transistor also rises, and the following problems may occur.
(a) The erase time becomes long because erase becomes difficult. Alternatively, the erase voltage must be set high because the erase threshold voltage (e.g., −2 V) becomes significantly different from the neutral threshold voltage and a large amount of charges must be injected to erase data to a desired erase threshold voltage.
(b) Since the erase threshold voltage becomes significantly different from the neutral threshold voltage, the high-temperature storage characteristic of erase data degrades. This is because, as described in (a), a larger amount of charges are held in the floating gate of a cell in the erase state, an electric field applied to a tunnel oxide film increases in data retention, and a small leakage current flowing through the tunnel oxide film increases during data retention.
Channel ion implantation may be executed in different steps for a cell transistor and selector gate transistor. However, it is not preferable in terms of complication and micropatterning of the manufacturing process to implant channel ions separately (in two steps).
As described above, in a conventional semiconductor device, it is very difficult to decrease the cell leakage current in write without degrading the erase characteristic and data retention characteristic.